1. Field of the Invention
This invention relates to semiconductor memories, and in particular to semiconductor memories having redundant columns which are as fast as the other columns in the semiconductor memory.
2. Description of the Prior Art
Numerous types of semiconductor read/write memories such as SRAMs, DRAMs, PROMs, EPROMs, EEPROMs, etc., are well known and commercially available. Such memories are typically arranged as rows and columns of memory cells, each cell within which is capable of storing a single bit of information--a zero or a one.
With advances in integrated circuit fabrication technology, the number of memory cells which may be placed on a single chip is increasing rapidly. These advances result from two factors--the capability of integrated circuit manufacturers to manufacture reliably larger chips, and the shrinking size of memory cells enabling more cells to be placed in a given area.
To further enhance the yield of integrated circuit chips containing memory cells, redundant rows and columns of memory cells have been developed, and are now well known. (To simplify the following explanation, the term "columns" is used rather than "rows or columns." It will be appreciated that either or both rows or columns may be employed, even though only columns are mentioned.) In a typical memory having redundant columns, extra columns are included on the chip with the regular columns; however, the spare columns are fusibly or otherwise selectively connectible in place of defective columns. In typical prior art systems, fuses are used to disconnect a defective column and other fuses to electrically replace the defective column with the spare column, program the address decoder of the redundant column, and perform any other necessary changes.
Although such prior art systems function satisfactorily in the sense that it is transparent to the system in which the memory is employed whether the information accessed is stored in a regular column or in a spare column, the use of spare columns carries with it several disadvantages. The primary disadvantage of spare columns is access speed.
The spare columns typically are slower than regular columns because of signal propagation delays. Because the spare columns are located to one side or the other of the memory array, all of the regular columns in the memory array will have a relatively short path length connection to an output node, while the spare columns will have a longer path to get the output data from the physical location of the redundant column output to its required destination at the output of the defective column. The longer path delays signal transmission between the spare columns and the exterior of the chip as compared to the regular columns. Because the access time of a memory must take into account the time required to obtain data from the slowest column, these delays result in slower access time for circuits in which the spare columns are employed, as compared to circuits in which they are not. The premium placed on high speed operation of memories makes this a substantial disadvantage.